One of the benefits of a using a MOSFET device is the high rate at which the device can be switched “on” and “off.” Faster switching allows for a more efficient device, but it also creates a higher voltage peak of the phase node when the device is switched into the “on” position. This voltage peak is also known as ringing. When used in a DC-DC application, the voltage peak of a phase node needs to be lower than 80% (or even much lower) of the device VDS rating in order for the device to maintain a high enough efficiency and avoid EMI issues. However, there is a trade-off between efficiency and ringing. Accordingly, gains in efficiency are made at the cost of an increase in the ringing.
The MOSFET's switching behavior is affected by the parasitic capacitances between the device's three terminals, that is, gate-to-source (CGS), gate-to-drain (CGD) and drain-to-source (CDS) capacitances. The MOSFET parasitic capacitances are commonly provided in the data sheet parameters as Ciss (Ciss=CGS+Crss), Coss (Coss=CDS+Crss), and Crss (Crss=CGD). Increases in Coss result in a reduction in the efficiency.
High values of Coss is always achieved through the use of SGT MOSFET devices. These devices typically have a Coss of around 250-350 pF per mm2. If an even higher Coss is desired, the designer can incorporate additional snubbers either within the device die or externally to reduce ringing. However, reductions in Coss to capacitances below 250 pF per mm2 for high efficiency are difficult to achieve due to the intrinsic snubber created by the shielded gate trench portion of the SGT MOSFET, which have an adjustable snubber resistor but a fixed Coss. Therefore, the optimum balance between efficiency and ringing is not always possible when using SGT MOSFETs due to high Coss.
In order to allow for more flexibility in device design, it would be preferable to start with a device that has a lower Coss. This would provide the designer a way to optimize the balance between the Coss and efficiency that will minimize ringing while still allowing for the efficiency required for a given set of design parameters. The use of a non-SGT MOSFET allows for this design option. A typical non-SGT MOSFET device has a Coss of about 100 pF per mm2. From this lower level of capacitance, there is a range of approximately 150 pF per mm2 in which the designer is able to alter the device Coss and snubber reisistor such that the voltage peak of a phase node does not exceed the maximum operating conditions for the device while still being able to maximize the efficiency of the device.
In a non-SGT MOSFET device the value of Coss can be increased by integrating a snubber circuit into the design. Snubber circuits are well known in the art and have been used to reduce ringing in MOSEFT devices. The snubber circuit is typically attached in parallel between the source and drain as an external component. Therefore, a snubber capacitor supplements the value of CDS of the MOSFET. Since CDS is a component of Coss, an increase in CDS will increase the value of Coss. However, snubbers have not previously been integrated into the die containing the MOSFET. Currently, snubber circuits are only partly integrated into MOSFET devices using the intrinsic source poly in the SGT device to provide an adjustable resistor but Coss is fixed. The ability to integrate the snubber circuit into the MOSFET would create advantages in the final product by allowing for more flexibility to increase or decrease the value of Coss and reduce the printed circuit board (PCB) area in the application circuit since there is no external snubber needed. Additionally, the integration of the dummy devices should preferably be accomplished without the use of additional mask layers in order to minimize the cost of fabrication.
It is within this context that embodiments of the present invention arise.